This invention pertains generally to semiconductor devices and, more particularly, to a fabrication process and structure in which capacitive coupling between conductors is minimized.
As semiconductor integrated circuits decrease in size and increase in speed, electrical interaction through capacitive coupling, or cross talk, becomes a limiting factor. As circuit conductors get closer together and/or switching speeds increase, capacitive coupling increases.
The capacitance between two conductors is directly proportional to the surface area of the sides of the conductors facing each other and the dielectric constant of the material between them, and inversely proportional to the spacing between the conductors.
Conventional insulators such as silicon dioxide (SiO2) have dielectric constants on the order of 4.0 to 4.6, and in order to reduce capacitive coupling, there have been some attempts to replace those insulators with materials having lower dielectric constants. Materials having dielectric constants on the order of 2.2 to 2.7 have been investigated in laboratories, but have not been used on a commercial basis. They only reduce the capacitance by a factor of about 2, and there are a number of other problems with them. Those problems include poor adhesion, inability to withstand chemical mechanical polishing (CMP), difficulty in anisotropic etching, poor stop selectivity over and under other films, low temperature ratings which limit subsequent process steps, and the need for protective liners to prevent the dielectric material from reacting with the metal conductors.
A few so-called ultra low K materials have also been investigated. Those materials have dielectric constants of about 2, and are subject to the same problems as the other alternative materials. In addition, they require new processes that are not well understood, they have low yields, and they require new process control and material delivery equipment.
There have been some attempts to use voids to reduce the capacitance between conductors, with the tops of the voids being pinched off as a result of non-conformal deposition. An example of a device made by this technique is illustrated in FIG. 1 where a void 11 is formed in the oxide 12 between conductors 13, 14. This process is not well controlled or uniform across the wafer, which causes the height and width of the voids to vary. The voids also vary in size and shape with changes in line spacing. These variations make the capacitive coupling unpredictable, which makes circuit design difficult or impossible.
It is in general an object of the invention to provide a new and improved semiconductor fabrication process and structure.
Another object of the invention is to provide a fabrication process and structure of the above character which significantly reduces capacitive coupling between conductors.
These and other objects are achieved in accordance with the invention by providing a semiconductor fabrication process and structure in which an evaporative material is deposited in a space between two conductors, a layer of porous material is formed adjacent to the evaporative material, and the evaporative material is evaporated through the porous material to leave a closed empty space between the conductors. The empty space has a dielectric constant on the order of 1.0, which minimizes capacitive coupling between the conductors.